1. Field of the Invention
The present invention relates to digital circuits design tools. In particular, the present invention relates to a design method in avoiding bus contention in a digital circuits.
2. Discussion of the Related Art
In a digital circuit, a frequently used bidirectional connection, referred to as a "bus", is shared by two or more devices for data transfer. In such a digital circuits the bus is typically shared synchronously, with each device being granted the use of the bus for the duration of a period of a clock signal. Ideally, a data bus driver granted the use of the bus would drive its data onto the bus through the end of the clock period, so as to allow the data to be latched at the beginning of the next clock period. Clearly, to achieve high performance, the bus should be available to the connected devices every clock period. Practically, however, a transient contention condition can occur when two devices drive the bus during successive clock periods, as illustrated below with reference to FIGS. 1a and 1b. As shown in FIG. 1a, a data bus 100 in the prior art is driven by two sets of data bus drivers 101 and 102, which are controlled by enable signals ENABLE.sub.-- A and ENABLE.sub.-- B at control terminals 103 and 104 respectively. Data bus drivers 101 and 102 drive data signals A and data signals B onto data bus 100. FIG. 1b is a timing diagram showing a clock signal CLOCK, signals ENABLE.sub.-- A and ENABLE.sub.-- B and the data signals, i.e. data signals A and data signal B, on data bus 100.
As shown in FIG. 1b, data signals A and data signals B are allocated the use of data bus 100 during periods 105 ("A cycle") and 106 ("B cycle") of clock signal CLOCK respectively. During the A cycle, at time t.sub.1, data signals A are ready and enable signal ENABLE.sub.-- A turns on data bus driver 101 to place data signals A onto data bus 100. Likewise, during the B cycle, at time t.sub.2, data signals B are ready and enable signal ENABLE.sub.-- B turns on data bus driver 101 to place data signals B onto data bus 100. Signal DATA of FIG. 1b is a timing representation of the placements of the data values onto bus 100. As shown in FIG. 1b, because of the different delay characteristics of the circuits generating enable signals ENABLE.sub.-- A and ENABLE.sub.-- B, the active periods of enable signals ENABLE.sub.-- A and ENABLE.sub.-- B overlaps (i.e. enable signal ENABLE.sub.-- A remains active until time t.sub.3, after enable signal ENABLE.sub.-- B has become active) whenever a B cycle follows an A cycle. Consequently, contention on data bus 100 occurs during time period (t.sub.2, t.sub.3), i.e. the overlap period during which enable signal ENABLE.sub.-- B becomes active and enable signal ENABLE.sub.-- A becomes inactive. Such contention is unacceptable if physical damage is caused to the bus drivers, or if data is read from the data bus during the overlap period (i.e. time interval (t.sub.2, t.sub.3)), thereby causing an integrity problem elsewhere in the digital system. In fact, even if enable signal ENABLE.sub.-- A becomes inactive at time t.sub.2, i.e., coincidentally with enable signal ENABLE.sub.-- B becoming active, variations in the delays of bus drivers 101 and 102 may still cause the bus contention problem described above.
Because of their complexities, which make computer simulations impractical, modern digital circuits are often verified and debugged using a hardware emulation system. A hardware emulation system implements a digital circuit on a programmable circuit board, using generic programmable logic integrated circuits, e.g. field programmable gate arrays (FPGAs), as surrogates. Typically, while allowing different portions of the digital circuit to be analyzed using both the hardware and the software of the emulation system, such an implementation are necessarily clocked at a reduced speed. As a result, some delay characteristics (e.g. tri-state bus turn-off times) can be ten or more times worse in the emulation circuit than in the actual target implementation. Thus, even if the target implementation is designed such that the bus contention has a tolerable duration, an unacceptable or destructive bus contention condition may occur in the emulation circuit.
In the prior art, to allow the logic circuit under design to be emulated, one way to avoid a destructive bus contention condition is to require that a "dead" cycle (i.e. a clock period during which the data bus is not used or "idled") to be inserted whenever a B cycle follows an A cycle. However, such a requirement clearly degrades system performance by introducing into the digital circuit an unnecessary delay of a clock period for each dead cycle. Alternatively, a destructive bus contention condition is avoided by redesigning the logic circuit, so that bus driver 101 turns off sooner, or bus driver 102 turns on later, relative to the beginning of the B cycle. Such a redesign is not always practical, and in fact undesirable, if the bus contention is unacceptable only in the emulation circuit, but not in the target implementation.